The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. This may include the use of a dual damascene process. A typical dual damascene process flow is as follows: IMD Deposition--> VIA Photo/Etch--> Metal pre-patterning--> Metal Trench Photo/Etch--> PVD Barrier (TaN etc)/Seed Dep. (Cu)--> Cu electroplating (ECP)--> Cu CMP
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulating layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner. The various layers define circuit components or devices such as transistors.
After the individual devices have been fabricated on the substrate, they must be connected together to perform the desired circuit functions. This interconnection process is generally known as “metallization” and is performed using a number of different photolithographic, deposition, and removal techniques. In a common interconnection process, two interconnect channels of conductor materials are separated by interlayer dielectric layers in vertically separated planes perpendicular to each other and interconnected by a vertical connection, or “via”, at their closest point
FIGS. 1A-1G illustrate sequential process steps carried out according to a conventional method to form a protective aluminum bonding pad and dual passivation layers for a top metal line in a conventional metal interconnect structure 10. The structure 10 typically includes multiple dielectric layers 12a-12f, respectively, which are sequentially deposited on a wafer substrate (not shown) and each other. A bottom metal line 16a, a middle metal line 16b and a top metal line 16c are formed in the dielectric layers 12b, 12d and 12f, respectively. Bottom vias 14a connect the bottom metal lines 16a to device features (not shown) fabricated in or on the wafer substrate. In similar fashion, middle vias 14b connect the middle metal lines 16b to the bottom metal lines 16a, and top vias 14c connect the top metal lines 16c to the middle metal lines 16b. 
As shown in FIG. 1A, after completion of a top metal line 16c, a bottom passivation stop layer 18 and a bottom passivation layer 20 are deposited on the top dielectric layer 12f and top metal line 16c. As shown in FIG. 1B, a photoresist layer 22 is then deposited on the bottom passivation layer 20 and patterned to form photoresist openings 23 corresponding to the location and size of a protective aluminum bonding pad to be subsequently formed. As shown in FIG. 1C, the bottom passivation layer 20 is then etched to form a pad opening 21 corresponding to the size and location of the photoresist opening 23. This is followed by stripping of the photoresist layer 22 from the bottom passivation layer 20 and removal of the bottom passivation stop layer 18 from the top metal line 16C. An aluminum pad 26 is next formed in the pad opening 21 of the bottom passivation layer 20, on top of the top metal line 16c, as shown in FIG. 1D. A photoresist layer (not shown) is provided on the aluminum pad 26, which is then etched in the desired configuration, after which the photoresist layer is stripped.
As shown in FIG. 1E, a top passivation layer 28 is next formed on the aluminum pad 26 and bottom passivation layer 20. As shown in FIG. 1F, a photoresist layer 30 patterned with an opening 31 is next formed on the top passivation layer 28, and the underlying top passivation layer 28 is etched to form an opening 29 therein. As shown in FIG. 1G, the photoresist layer 30 is next stripped from the top passivation layer 28. Finally, SiON is removed from the pad 26, followed by argon treatment and wet stripping to remove residual polymer residues from the structure 10. The top passivation layer 28 prevents inadvertent scratching and peeling of the aluminum pad 26, whereas the aluminum pad 26 prevents corrosion of the top metal line 16c. 
Packaging follows in which an IC chip (not shown) of which the interconnect structure 10 is a part is assembled into a higher-order electronic structure. This involves the wire bonding of an internal lead (not shown) of a leadframe to the aluminum pad 26. The leadframes are electrically attached to components in the electronic structure.
The dual passivation process heretofore described with respect to FIGS. 1A-1G requires 13 separate process steps and contributes to an excessively long cycle time. Furthermore, the process results in a high fluorine concentration in the aluminum pad 26, increasing the likelihood of pad crystal (F-pad) defects which may cause bondability failure during subsequent chip packaging.
Therefore, a method of reducing the number of process steps required for the top metal interconnect lines' associated protective/bonding structures formed on a semiconductor wafer is needed.
Accordingly, an object of the present invention is to provide a method which includes the formation of a protective plate which is bounded by a passivation layer to protect a top metal interconnect line in a metal interconnect structure from oxidation, corrosion, scratching and peeling.
Another object of the present invention is to provide a method which simplifies the process used to form top metal interconnect lines associated protective/bonding structures, thus substantially reducing the process cycle time.
Still another object of the present invention is to provide a method which eliminates the need to use a dual passivation scheme to avoid aluminum pad scratching and peeling.
Yet another object of the present invention is to provide a method which eliminates the need to use an aluminum pad and dual passivation structure to prevent corrosion of a top metal line by using a protective plate bounded by a passivation layer to protect the top metal line.